In order to test the normal operation lifetime of a semiconductor memory device under actual circumstances, a huge amount of time is required. It is important to shorten a test time while precisely predicting the operation lifetime of the semiconductor memory device. To meet this need, a burn-in test is employed.
In the burn-in test, a word line of a semiconductor memory device is activated with a voltage higher than a normal operation voltage and under circumstances with a temperature higher than a normal operation temperature, stresses are repeatedly applied by performing a write operation and a precharge operation for a memory cell, and then, pass/fail of the memory cell is tested.
An operation of such a burn-in test to apply stresses to a memory cell will be described below with reference to FIG. 1.
FIG. 1 is a timing diagram explaining an operation for performing a burn-in test of a conventional semiconductor memory device.
First, a semiconductor memory device performs an active operation ACT at a time T1, in which a word line is activated according to a combination of external commands RASB, CASB and WEB and an address ADD inputted in synchronization with an external clock CLK inputted from external test equipment.
Next, the semiconductor memory device performs a write operation WT at a time T2, in which the data inputted through a DQ pad DQ are written to a memory cell according to a combination of the external commands RASB, CASB and WEB and the address ADD inputted in synchronization with the external clock CLK.
Then, the semiconductor memory device performs a precharge operation PCG at a time T3, in which a bit line is precharged according to a combination of the external commands RASB, CASB and WEB and the address ADD inputted in synchronization with the external clock CLK.
Thereupon, the semiconductor memory device performs, at a time T4, the active operation ACT the same as that at the time T1 and then repeatedly performs the write operation WT and the precharge operation PCG to apply stresses to the memory cell.
Such a burn-in test of the semiconductor memory device is performed in synchronization with the external clock CLK. However, when the operation speed of the external test equipment is slow, the frequency of the external clock CLK is low, and as the frequency of the external clock CLK is low, a time for performing the burn-in test is lengthened.